The breakthrough that makes silicon nanonets a real opportunity for electrical devices!
According to the literature, the presence of native oxide shell surrounding silicon nanowires impedes the carrier transfer from one nanowire to another through their junction. As a consequence, such phenomenon is the main reason that limits the manufacturing of electrical devices based on assembly of Si nanowires, also called nanonet.
Contrary to this bias, we patented a simple and efficient process that allows us to overcome the above issue and moreover, stabilize nanowire/nanowire junctions. Two characterizations were carried out to demonstrate the efficiency of our process: a) the conductivity measurement over time of devices when stored in air; b) the microstructural observation of nanowire/nanowire junction under high-resolution transmission electron microscope.
As illustrated in the graph, the device, after being sintered by our process, exhibits an almost constant conductance with time. On the other hand, absence of such sintering implies the continuous decrease of device conductance until reaching an isolating behavior. Additionally, as shown from transmission electron microscopy micrographs, a neck formation at sintered nanowire/nanowire junction is observed that reveals the continuity of the silicon crystalline network between the two nanowires. This microstructural observation demonstrates the undoubtable impact of our sintering process by turning the assembly of juxtaposed silicon nanowires to a polycrystalline network.
Our patented process is the combination of two effects:
removal of native oxide surrounding Si nanowires,
afterwards, sintering of these nanowire/nanowire junctions by low temperature annealing (400°C).
Its great advantage is the compatibility with the back-end of CMOS process which opens a new route for 3D integration of nanonet-based devices.